1. Field of the Invention
The present invention relates generally to A/D converters. More specifically, the invention relates to an A/D converter having an improved arrangement of voltage comparators.
2. Description of the Background Art
FIG. 4 is a circuit diagram showing a conventional A/D converter. In FIG. 4, there are provided N voltage comparators C.sub.1, C.sub.2, . . . , C.sub.N, each of which includes first to fourth input terminals T.sub.1 -T.sub.4 and an output connected to encoder 1. There are provided a ladder of N+1 resistors r.sub.1, r.sub.2, . . . , r.sub.N/2, r.sub.N/2+1, . . . r.sub.N, and r.sub.N+1 connected in series, one end of which is provided with a first reference voltage V.sub.RT, and the other is provided with a second reference voltage V.sub.RB. Intermediate taps are provided at connection points of ladder resistors r.sub.1, r.sub.2 . . . , r.sub.N/2, r.sub.N/2+1, . . . , r.sub.N, and r.sub.N+.sub.1.
The first terminal T.sub.1 of voltage comparator C.sub.1 is connected to a first intermediate tap which is a connection point between ladder resistors r.sub.1 and r.sub.2, and the second terminal T.sub.2 of voltage comparator C.sub.1 is connected to the N-th intermediate tap which is a connection point between ladder resistors r.sub.N and r.sub.N+1. The first terminal T.sub.1 of voltage comparator C.sub.2 is connected to a second intermediate tap, and the second terminal T.sub.2 is connected to the (N-1)-th intermediate tap. Similarly, voltage comparators C.sub.N/2, C.sub.N/2+1 . . . , C.sub.N-1, and C.sub.N are each connected to a prescribed intermediate tap. The third terminals T.sub.3 and fourth terminals T.sub.4 of voltage comparators C.sub.1 -C.sub.N are connected together, each third terminal T.sub.3 is provided with a positive side input voltage V.sub.i and each fourth terminal T.sub.4 is provided with a negative side input voltage V.sub.i. Voltage comparators C.sub.1 -C.sub.N are each provided with a clock signal .phi..
Voltage comparators C.sub.1 -C.sub.N each compare differential input voltages V.sub.i and V.sub.i input to third and fourth terminals T.sub.3 and T.sub.4, and a reference voltages input to first and second terminals T.sub.1 and T.sub.2. At the time, if an input voltage is larger than a differential voltage applied to the m-th voltage comparator, and smaller than a reference differential voltage applied to the (m+1)-th voltage comparator, the outputs of the first to m-th voltage comparators attain an "H" level, and the outputs of the (m+1)-th to the N-th voltage comparators attain an "L" level. Accordingly, in view of the output of each voltage comparators C.sub.1 -C.sub.N, which differential reference voltage a differential input voltage is larger than can be known, and the larger differential input voltage is passed through encoder 1 for A/D conversion.
In an A/D converter using conventional differential comparators is configured as illustrated in FIG. 4, a large amount of wiring is necessary for applying the intermediate tap voltages of ladder resistors r.sub.1 -r.sub.N+1 to voltage comparators C.sub.1 -C.sub.N, resulting in increase of the area occupied by the chip.